A 0.84ps-LSB 2.47mW Time-to-Digital Converter Using a Charge Pump and a SAR-ADC
نویسندگان
چکیده
We propose a time-to-digital converter (TDC) using a charge pump and a SAR-ADC. With this architecture, high time resolution is attainable by increasing the charging current or reducing the sampling capacitance. Thus, the resolution limitation in a delay-chain TDC does not exist. We propose to use a SAR-ADC attributed to its characteristics of compact structure, scalability, low power consumption, and small area. The prototype chip was fabricated in 65nm CMOS, achieving 0.84ps LSB, 2.47mW power consumption, and 0.06mm area occupation. With 8-bit outputs, the DNL and INL are -0.7/1.0 LSB and -2.7/1.7 LSB, respectively.
منابع مشابه
A 0 . 8 ps - LSB , 10 - bit , 0 . 018 mm 2 Time - to - Digital Converter
A time-to-digital converter, using a charge pump to translate time interval into charge and a SAR-ADC quantizing the charge, can achieve sub-picosecond resolution. To improve the linearity and area occupation, we propose a sampling method and a layout pattern for the capacitive DAC in the SAR-ADC. The prototype chip was fabricated in 65nm CMOS. The measured DNL and INL are -0.6/0.8 ps and -2.56...
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